This invention relates in general to the field of semiconductor manufacturing and, more particularly, to a test wafer and method for monitoring electrostatic discharge induced wafer defects.
Over the past several years, the development of electronic devices such as laptop computers, hand held computers, personal data assistants (PDA) and global telephones has resulted in an increased demand for smaller semiconductor integrated circuits (IC) and associated electronic components. In order to meet this demand, manufactures have developed several techniques to reduce the overall size and dimensions of an electrical component. Specifically, some of these techniques are aimed at circuit geometries that include smaller and more dense electrical components.
The manufacturing of complex semiconductor devices involves a series of processes including deposition, inspection, photolithography, etching, and testing. During the photolithographic process, semiconductor manufacturers use a photomask to copy an image of an electronic circuit on to a semiconductor wafer. Photomasks generally include a transparent substrate having a patterned metal layer (e.g., chrome) deposited on one surface. This patterned metal layer contains the microscopic image of the electrical circuit, which may be referred to as the photomask""s geometry.
Ideally, the patterning process creates exact replicas of the desired electrical circuit on the wafer. However, there are several factors which affect the quality of the geometry, including any electrical parameters. The quality of the geometry created on the wafer, as well as electrical parameters of the various layers that form the geometry, will substantially dictate the quality of the electronic circuits. As design rules have moved toward smaller and more dense IC devices, the integrity of the geometry, and the associated electrical parameters have become increasingly important.
One key cause of geometry degradation is electrostatic discharge (ESD). ESD is created when a force causes a charge imbalance between conductive features on a semiconductor wafer. In the semiconductor context, effects of ESD include material sputtering and material migration. Instances of these effects can result in the non-functioning of IC devices created from a degraded semiconductor wafer. As such, an incentive exists for identifying problem wafers and potential sources of ESD. Unfortunately, given the large number of process steps necessary to create a large scale IC device, it is often very difficult to identify and monitor ESD effects throughout the complete manufacturing process. This is especially true when wafer production, handling, storage and cleaning are included in the list of semiconductor manufacturing process steps.
One conventional method of testing for ESD damage on wafer is a functionality test. Typically, ESD damage on a semiconductor wafer attacks the functionality of a single transistor in an IC device. Functionality testing for ESD damage is performed at the end of the manufacturing process by using s completed electrical circuit on the semiconductor wafer. Electrical measurements are taken to test the circuit pathways to determine possible ESD damage. The functional test, however, retroactively identifies potential ESD effects because the test uses a completed semiconductor IC.
While a defect inspection is another conventional method of testing, this technique typically focuses more on the photomask used to create the image on the wafer. Defect inspection may include either a die-to-die inspection or die-to-database inspection. In either case, an actual photomask geometry is compared to an ideal photomask geometry. Differences between the actual and the ideal are identified and a determination as to defect severity is made. Typically, the inspection may include a performance check of different resist structures, which have been created during a photolithography process or may appear following an etching step. Again, the inspection technique is retroactive since it identifies defective dies after they have been damaged. Furthermore, the method is difficult to apply to wafers because of the number of different electrical patterned layers that may be incorporated on the semiconductor IC. Moreover, the inspection method requires a costly device that is capable of comparing the actual geometry with the ideal geometry.
A further inspection method includes taking electrical field strength measurements at various steps during a semiconductor manufacturing process. This method is problematic for at least two reasons. First, electrical field strength measurements are not ESD measurements. The strength of an electrical field is merely an indicator of ESD potential. And second, the measurement is merely an indication of the ESD potential associated with a particular process. The ESD effects induced during the particular process may be only one component of the total ESD effects that a typical wafer encounters.
In accordance with teachings of the present invention, the disadvantages and problems associated with testing for and investigating electrostatic discharge (ESD) induced wafer defects have been substantially reduced or eliminated. In a particular embodiment, a method for investigating ESD induced wafer defects is disclosed that includes analyzing a test wafer using an ESD sensitive risk scale geometry to identify and evaluate severity of electrostatic discharge effects associated with a semiconductor manufacturing procedure.
In accordance with one embodiment of the present invention, a method for investigating ESD induced wafer defects includes exposing a test wafer that includes an ESD sensitive risk scale geometry to a semiconductor manufacturing process and analyzing the test wafer using the risk scale geometry to identify and evaluate severity of ESD effects associated with the manufacturing process. The test wafer, which contains an ESD sensitive geometry, is exposed to one or more semiconductor manufacturing processes. After exposure, the test wafer may be analyzed using the risk scale geometry to determine how much, if any, degradation of the geometry has occurred as a result of the exposure.
In accordance with another embodiment of the present invention, a method for monitoring severity of ESD effects includes contacting a test wafer having an ESD sensitive risk scale geometry with a piece of semiconductor manufacturing equipment. The wafer may then be removed from the piece of semiconductor manufacturing equipment. The ESD sensitive geometry on the wafer is analyzed using the risk scale geometry to determine severity of degradation, if any, of the geometry that occurred as a result of contact with the semiconductor manufacturing equipment.
In accordance with a further embodiment of the present invention, an apparatus for investigating ESD induced wafer defects includes a wafer that includes a plurality of test modules which define a risk scale. The plurality of test modules includes ESD sensitive geometry formed on the wafer defined in part by bodies with sufficient surface area to induce ESD effects. The geometry may include a line and a gap disposed between the bodies. In one particular embodiment, the apparatus may be formed from a string of test modules that are arranged such that the line associated with a first module extends towards the body associated with a second module.
Important technical advantages of certain embodiments of the present invention include an ESD sensitive geometry formed on a test wafer. The ESD sensitive geometry includes a body feature sufficient to induce an ESD effect with a line extending towards a second body feature and a gap formed between the line and the second body. The ESD sensitive geometry allows the test wafer to reveal ESD effects in one or more cycles of exposure to a given manufacturing procedure or manufacturing device.
Another important technical advantage of certain embodiments of the present invention includes an ESD sensitive geometry that corresponds to one or more design rules in a semiconductor manufacturing process. A design rule sets minimum allowable feature sizes for electrical circuits used to create an IC device. The ability of the ESD sensitive geometry to relate to multiple design rules allows a manufacturer to quickly determine what design rule can consistently be used with the existing manufacturing tools to manufacture the IC device.
A further technical advantage of certain embodiments of the present invention includes an ESD risk scale geometry that allows users to identify, monitor and evaluate a single process step (e.g., photolithography, cleaning, etc.) in a semiconductor manufacturing process. Alternatively, the user may identify, monitor and evaluate the entire semiconductor manufacturing process and associated wafer handling procedures for cumulative ESD effects. The user, therefore, may quickly identify ESD problem areas in the semiconductor manufacturing process.